A solid-state image sensing device, such as a charge-coupled device, responds to incident light to generate signal charges that are stored in a depletion region and produce an output signal at an output terminal thereof. A basic charge-coupled device includes a metal-oxide semiconductor device in which a metal electrode is positioned on, and insulated from, a silicon substrate. Charge-coupled devices, or solid picture elements, are arranged in arrays and coupled to circuitry that samples the devices for use in, for example, generating a video image.
In recent years, to increase the sensitivity of picture elements, several types of elements known as amplifier type picture elements have been disclosed in which a transistor for amplifying signals is installed. An example of this is disclosed by Japanese unexamined patent application no. 8-293591. The elements disclosed by this patent application are several examples in which a charge accumulation portion that accumulates charges produced in response to light incident on a light receiving part and an amplifying transistor that outputs signals in response to charges detected are formed in separate locations, and a transfer gate is installed between these to control the transfer of charges from the charge accumulation portion to the amplifying transistor. Of these, examples are disclosed in which the photodiode of the light receiving part is a buried photodiode (BPD), and in which the amplifying transistor is a junction field effect transistor (JFET).
FIG. 13 shows a schematic plan of a unit pixel of a prior art solid picture element. In addition, FIG. 18 shows an example of an overall circuit structure of a solid picture element.
The prior art solid picture element, shown in FIG. 13, is comprised of parts that include BPD 301 that is a light receiving part or photoelectric converter part, JFET 302 that amplifies the photoelectrically converted charge, transfer gate 303 that controls transfer of charges from BPD 301 to JFET 302, reset drain 304 that applies a reset potential to the JFET gate, and reset gate 305 that controls the JFET reset operation.
FIG. 14 is a cross section of the solid picture element shown in FIG. 13 taken along line X-X'.
As shown in FIG. 14, N-type well 202 is formed in P-type substrate 201. Formed in this N-type well 202 are BPD P-type charge accumulation layer 203 and N-type depletion prevention layer 204, P-type gate 205 used as the JFET gate on the substrate surface, N-type channel 206 used as the JFET channel, deep P-type gate 207 used as the JFET gate below the channel, N-type source 208 used as the JFET source, and N-type drain 209 used as the JFET drain and as an element separator.
Because normally each of these regions is formed by implanting ions selectively into the surface of semiconductor substrate 201, then heating and diffusing the substrate, the impurity concentration becomes lower the deeper the layer is in the semiconductor substrate, and the impurity concentration also is reduced gradually by horizontal diffusion in the region close to the edge of masks during ion implantation. Transfer gate 210, which is an electrode that controls transfer of charges on the surface of substrate 201 from the BPD to the JFET, is installed on an insulating film (not shown in the figure), such as silicon oxide film. In addition, connecting parts (not shown) connect P-type gate 205 to deep P-type gate 207, and N-type well 202 to N-type depletion prevention layer 204 to maintain gate 205 and deep gate 207, and well 202 and layer 204, at the same potential. Furthermore, FIG. 14 does not show an aluminum, or similar, pattern that is connected to JFET N-type source 208.
Generally, prior art solid picture elements or the type of FIG. 14 are fabricated by a method such as shown schematically in FIGS. 17a-17c. FIGS. 17a-17c do not show regions corresponding to JFET 302, reset drain 304, and rest gate 305 in FIG. 14.
With reference to FIGS. 17a-17c, N-type well 202 is formed in P-type semiconductor substrate 201, and a protective oxide film 214, a relatively thin insulating film, is formed on the surface of substrate 201 either before or after forming N-type well 202. Resist mask 215 is formed on the protective oxide film 214 on the surface of substrate 201. By implanting P-type ions 221 near the surface of substrate 201, and using resist mask 215 as a mask, then heating and diffusing the substrate, BPD P-type charge accumulation layer 203 is formed in N-type well 202 (FIG. 17(a)).
By implanting N-type ions 222 near the surface of substrate 201 using the same resist mask 215 as a mask, then heating and diffusing the substrate, N-type depletion prevention layer 204 is formed in P-type charge accumulation layer 203 (FIG. 17(b)). P-type charge accumulation layer 203 and N-type depletion prevention layer 204 also can be formed by heat diffusion by implanting P-type ions 221 and implanting N-type ions 222, then performing heat treatment all at once.
Resist mask 215 is then removed, gate oxide film 213 is formed on the surface of substrate 201 (e.g., by making the thickness of protective oxide film 214 thicker) and transfer gate 210 is formed of a material such as polysilicon on gate oxide film 213 (FIG. 17(c)).
P-type charge accumulation layer 203 and N-type depletion prevention layer 204 also can be formed by implanting P-type ions or N-type ions without using resist mask 215 by using at least part of transfer gate 210 as a mask. But, in either case, the edge of the mask when used to implant ions to form P-type charge accumulation layer 203 is either in the same position as, or closer to, the JFET than the edge of the mask when used to implant ions to form N-type depletion prevention layer 204.
Next, the prior art charge transfer operation, from P-type charge accumulation layer 203 to the JFET in this type of solid picture element, is explained.
As an example, substrate potential is set to 0 V and N-type well 202 and N-type depletion prevention layer 204 are set to 5 V When a charge has accumulated on the BPD, transfer gate 210 is set to 5 V and placed in OFF state. In addition, by setting reset gate 305 to an ON state by applying a voltage and setting reset drain 304 to -5 V, the JFET P-type gate becomes the same -5 V as the potential of reset drain 304, and the JFET is placed in an OFF state. Because the part of P-type charge accumulation layer 203 that contacts the surface of semiconductor substrate 201 is inverted to N-type at this time, the speed of generation of noise current in this part is slow. Charge accumulates in BPD P-type charge accumulation layer 203 and the potential of P-type charge accumulation layer 203 rises, and when this reaches a certain level of potential or higher, the charge overflows into the substrate.
When a charge is transferred from the BPD to the JFET, first, by placing reset gate 305 in an ON state and setting reset drain 304 to -2 V, the JFET P-type gate 205 is set to -2 V. Next, by placing reset gate 305 in an OFF state, the JFET P-type gate 205 becomes floating. Next, transfer gate 210 is set to -2 V and placed in ON state, and the charge is transferred from BPD P-type charge accumulation layer 203 to JFET P-type gate 205.
As charges are transferred to P-type gate 205 and deep P-type gate 207, the potential of P-type charge accumulation layer 203 drops and the potential of JFET P-type gate 205 and deep P-type gate 207 rises. When the potential of JFET N-type source 208 is set, for example, to approximately 0 V by a read circuit (not shown in the figure) and the potential of JFET P-type gate 205 exceeds approximately 0 V, the PN junction reverses direction and the charge is expelled to JFET N-type source 208. As a result, the potential of JFET P-type gate 205 rises only to a peak of approximately 0 V. Therefore, when P-type charge accumulation layer 203 is set to a depletion voltage of approximately 5 V or less, P-type charge accumulation layer 203 can be depleted by this type of charge transfer operation.
FIG. 15 shows the distribution of potential along charge transfer route OPQRS from BPD P-type charge accumulation layer 203 to JFET P-type gate 205 during charge transfer in FIG. 14. In addition, FIG. 16 shows the distribution of impurity concentration in the horizontal direction across positions T, U, and V in FIG. 14.
When P-type charge accumulation layer 203 is formed by heating and diffusing P-type ions implanted close to the surface of substrate 201, the impurity distribution near the edge of P-type charge accumulation layer 203 (corresponding to position U) becomes uneven and decreases gradually as shown in FIG. 16 from position T to position U. As a result, potential near this edge rises and produces a spike 22 in potential as shown by the curve from O to P in FIG. 15. In addition, in the region below transfer gate 210, because potential drops in the P-type part and rises in the N-type part as shown by P to R in FIG. 15, this produces a trough 24 in potential near point P on the charge transfer route.
When the size of the overlap shown in FIG. 14 is reduced--that is, when the distance on the surface of N-type well 202 from the edge of N-type depletion prevention layer 204, that faces the JFET to the edge of P-type charge accumulation layer 203 that faces the JFET is reduced, this trough 24 in potential is reduced, but the spike 22 in potential is increased. Conversely, when the overlap shown in FIG. 14 is increased, the spike in potential is reduced, but the trough in potential is increased. As a result, this type of trough and spike in potential cannot be eliminated simultaneously simply by controlling the size of overlap. Because this type of trough and spike in potential could not be completely eliminated, prior art solid picture elements have the problem that they are unable to transfer charges completely from the BPD to the JFET. This causes residual images.
In addition, in prior art fabrication of solid picture elements, P-type charge accumulation layer 203 and N-type depletion prevention layer 204 are formed by implanting ions using the same mask, then controlling heat treatment. However, this is a problem because the impurity ions that form P-type charge accumulation layer 203 and N-type depletion prevention layer 204 have different diffusion coefficients. Thus, the amount of horizontal diffusion differs for each type of ion, or is difficult to control, and it is difficult to control the size of overlap precisely.
In addition, when an overlap is formed by the difference in amount of horizontal diffusion caused by the difference in diffusion coefficients, forming an overlap of about 0.4 micrometers, for example, requires excessive heat treatment and is imprecise. This excessive heat treatment affects other diffusion layers or causes wafer warping, and furthermore risks causing discrepancies in element characteristics.
A preferred embodiment of the present invention solves the problems of prior art devices by providing a solid picture element having a semiconductor substrate region (a well formed in a semiconductor substrate) of a first conductive type, a charge accumulation region of a second conductive type installed within the semiconductor substrate region, a depletion prevention region of the first conductive type installed in between the charge accumulation region and the surface of the semiconductor substrate region, a transistor for amplifying charges that is installed in a region within the semiconductor substrate region proximate the charge accumulation region and depletion prevention region, and a transfer gate, located on the surface of the semiconductor substrate region between the region where the depletion prevention region is installed and the region where the transistor is installed, that controls transfer of charges from the charge accumulation region to the transistor region.
The solid picture element is constructed such that an edge of the charge accumulation region that is closest to the transistor is located below the transfer gate, and an edge of the depletion prevention region that is closest to the transistor is located inline or further from the transistor than the charge accumulation region and the charge accumulation region does not contact the surface of the semiconductor substrate region. By this type of structure, charges can be transferred from the charge accumulation region of the photodiode to the amplifying transistor in a solid picture element, and residual images can be substantially eliminated.
In a preferred embodiment, the transfer gate is a metal-oxide semiconductor (MOS) gate.
In a preferred embodiment, the transistor can be a junction field effect transistor (JFET). Alternatively, the transistor can be constructed as a bipolar transistor. Or, alternatively, the transistor can be constructed as a MOS transistor. Either preferred embodiment makes it possible to increase the sensitivity of the solid picture element accurately.
Preferably, this solid picture element is constructed such that the edge of the charge accumulation region nearest the transistor is 0.0 to 0.2 .mu.m closer to the transistor than the edge of the depletion prevention region that is nearest to the transistor. Because there is no trough or spike in potential in the charge transfer route from the charge accumulation region to the transistor during charge transfer in the present invention, it is possible to transfer charges completely and accurately and to substantially eliminate residual images securely.
In addition, this invention offers a method of manufacture of a solid picture element that has a semiconductor substrate region (a well formed on a semiconductor substrate) of a first conductive type, a charge accumulation region of a second conductive type installed within the semiconductor substrate region, a depletion prevention region of the first conductive type installed between the charge accumulation region and an upper surface of the semiconductor substrate region, a transistor for amplifying charges installed in a region within the semiconductor substrate region that faces the charge accumulation region and depletion prevention region, and a transfer gate that is installed on the upper surface of the semiconductor substrate region between the region where the depletion prevention region is installed and the region where the transistor is installed and that controls transfer of charges from the charge accumulation region to the transistor region. A preferred method of manufacture of the solid picture element includes implanting ions of the second conductive type at an angle to the upper surface of the semiconductor substrate region using the transfer gate as a mask and to form the charge accumulation region such that it is within the semiconductor substrate region and does not contact a surface of the semiconductor substrate region, and a step to implant ions of the first conductive type at an angle to the semiconductor substrate region that is closer to perpendicular to the upper surface than the angle at which the ions of the second conductive type were implanted using the transfer gate as a mask and to form the depletion prevention region such that it is between the charge accumulation region and the upper surface of the semiconductor substrate region, and the edge of the charge accumulation region that faces the transistor is closer to the transistor than the edge of the depletion prevention region that faces the transistor. By this means, the charge accumulation region and the depletion prevention region can be formed to the desired profile with good control, and a solid picture element can be manufactured easily that can transfer charges completely from the charge accumulation region of the photodiode to the amplifying transistor and substantially eliminate residual images.
In addition, this invention provides an alternative embodiment of a method of manufacture of a solid picture of the present invention including the steps of implanting icons of the second conductive type into the semiconductor substrate region using the transfer gate as a mask and to form the charge accumulation region such that it is within the semiconductor substrate region and does not contact the surface of the semiconductor substrate region, and installing an insulating film to increase the footprint of the transfer gate on the upper surface and then implanting ions of the first conductive type into the semiconductor substrate region using the transfer gate covered by the insulating film as a mask to form the depletion prevention region such that it is between the charge accumulation region and the upper surface of the semiconductor substrate region such that the edge of the charge accumulation region that faces the transistor is closer to the transistor than the edge of the depletion prevention region that faces the transistor. By this means, the charge accumulation region and the depletion prevention region can be formed to the desired profile with good control, and a solid picture element can be manufactured easily that can transfer charges completely from the charge accumulation region of the photodiode to the amplifying transistor and substantially eliminate residual images.
In addition, this invention provides an alternative embodiment of a method of manufacture of a solid picture element of the present invention including the steps of implanting ions of the second conductive type into the semiconductor substrate region using the transfer gate as at least part of a mask and to form the charge accumulation region such that it is within the semiconductor substrate region and does not contact the upper surface of the semiconductor substrate region, forming insulating film on the semiconductor substrate region and transfer gate, etching the insulating film to form a side wall insulating film on the side walls of the transfer gate, and implanting ions of the first conductive type into the semiconductor substrate region using the side wall insulating film as a mask and as a result to form the depletion prevention region such that it is between the charge accumulation region and the surface of the semiconductor substrate region and whereby the edge of the charge accumulation region that faces the transistor is closer to the transistor than the edge of the depletion prevention region that faces the transistor. By this means, the charge accumulation region and the depletion prevention region can be formed to the desired profile with good control, and a solid picture element can be manufactured easily that can transfer charges completely from the charge accumulation region of the photodiode to the amplifying transistor and substantially eliminate residual images.
In addition, this invention provides another alternative embodiment of a method of manufacture of a solid picture element including the steps of forming a mask layer on the semiconductor substrate region, implanting ions of the second conductive type into the semiconductor substrate region using the mask layer as a mask and to form the charge accumulation region such that it is within the semiconductor substrate region and does not contact the upper surface of the semiconductor substrate region, removing the mask layer, forming the transfer gate on the semiconductor substrate region such that the position of the edge of the transfer gate on the side of the charge accumulation region is closer to the charge accumulation region than the position of the corresponding edge of the mask layer, and implanting ions of the first conductive type into the semiconductor substrate region using the transfer gate as at least part of a mask to form the depletion prevention region such that it is between the charge accumulation region and the upper surface of the semiconductor substrate region, and the edge of the charge accumulation region that faces the transistor is closer to the transistor than the edge of the depletion prevention region that faces the transistor. By this means, the charge accumulation region and the depletion prevention region can be formed to the desired profile with good control, and a solid picture element can be manufactured easily that can transfer charges completely from the charge accumulation region of the photodiode to the amplifying transistor and substantially eliminate residual images.